SCENARIO
SCENARIO = MODE + CORNER.
MODE: MODE IS DEFINED AS A SET OF CLOCKS , SUPPLY VOLTAGES ,TIMING CONSTRAINTS AND LIBRARIES.
MODES TYPE:
______________ NOMINAL
IT CONTAINS SDC CONSTRAINTS.
IN DESIGN DIFFERENT FUNCTIONALITY MODES CONTAINS DIFFERENT SDC'S.
IN DESIGN DIFFERENT FUNCTIONALITY MODES ARE PRESENT.
CONSTRAINTS IN TEST MODE WHILE THE CHIP IS A DEVICES UNDER TEST:
______________WORST CASE CORNER.
FOR SETUP :
Arrival Path-------- |
|--------------------->Max Dealys
Data path------------|
Reqired Path------------------------------->Min Delays
FOR HOLD :
Arrival Path-------- |
|--------------------->Min Dealys
Data path------------|
Reqired Path------------------------------->Min Delays
BEST CASE : --------->FASTEST<-------->MIN DELAYS<------->Early<-----------> FOR HOLD
SCENARIO = MODE + CORNER.
MODE: MODE IS DEFINED AS A SET OF CLOCKS , SUPPLY VOLTAGES ,TIMING CONSTRAINTS AND LIBRARIES.
MODES TYPE:
- FUNCTIONAL MODE.
- TEST MODE.
- RV MODE
_____________ HIGH
|
MODES --- _____________ LOW
|______________ NOMINAL
IN DESIGN DIFFERENT FUNCTIONALITY MODES CONTAINS DIFFERENT SDC'S.
IN DESIGN DIFFERENT FUNCTIONALITY MODES ARE PRESENT.
CONSTRAINTS IN TEST MODE WHILE THE CHIP IS A DEVICES UNDER TEST:
- TESTER CLOCK PERIOD AND CLOCK SOURCES.
- MODEL TESTER SKEW ON THE INPUT PORTS.
- DIFFERENT TIMING EXCEPTIONS.
- DIFFERENT SETUP/HOLD ON THE OUTPUT PORTS.
- THE SCAN CHAIN IS EXCERSIED IN TEST MODE.(NOT IN FUNCTIONAL MODE).
CORNERS:
CORNERS CONTAINS PVT'S.
_____________ BEST CASE CORNER
|
PVT -------------
|______________WORST CASE CORNER.
FOR SETUP :
Arrival Path-------- |
|--------------------->Max Dealys
Data path------------|
Reqired Path------------------------------->Min Delays
FOR HOLD :
Arrival Path-------- |
|--------------------->Min Dealys
Data path------------|
Reqired Path------------------------------->Min Delays
BEST CASE : --------->FASTEST<-------->MIN DELAYS<------->Early<-----------> FOR HOLD
- MIN DELAYS IN ARRIVAL PATH,DATA PATH .
- MAX DELAYS IN CLOCK PATH.
PVT: PROCESS---------------------->FAST
VOLTAGE--------------------->HIGH
TEMPERATURE------------>LOW
WORST CASE: --------->SLOWEST<-------->MAX DELAYS<------------> FOR SETUP
- MAX DELAYS IN ARRIVAL PATH, DATA PATH.
- MIN DELAYS IN CLOCK PATH.
PVT: PROCESS-------------------->SLOW
VOLTAGE-------------------->LOW
TEMPERATURE----------->HIGH
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